A few years ago, I wrote an article titled Memory Storage about future memory technologies. That article discussed molecular memory, phase change memory, holographic memory, and magneto-resistive RAM. In this article I thought I’d revisit that article and expand a bit on the section discussing phase change memory. This will also give me a chance to introduce some advances in the technology recently announced by IBM.
To understand the new advances made by IBM researchers you’ll need to know the basic science behind phase change memory and the challenges associated with it. Phase change memory is really very similar to the technology used in CD-R and DVD-R technologies.
In optical disc writing, a laser changes the opacity of small regions on the disc. The laser can make the small region more opaque or less opaque. It does this by changing the material from an amorphous state to a crystalline state or from a crystalline state to an amorphous state. When a disc reader then reads the reflection from the disc the reader will be able to determine if the region is in an amorphous or a crystalline state thus reading either a logical ‘1’ or a logical ‘0’.
Likewise, phase change memory also changes a small region from an amorphous state to a crystalline state and back again. In phase change memory implementations though, this change is done via an electrical current instead of a laser. More precisely, it is the heat that can change the state the optical disc and phase change memory implementations merely change how that heat is created/distributed. In my previous article Memory Storage, I highlighted the scientific similarities of resistivity to opacity, which even includes reflection!
Phase change memory systems can determine whether a region, often called a cell, is in an amorphous or crystalline state by measuring its electrical resistivity. This leads to one of the major advantages of a phase change memory system; the resistivity levels of amorphous and crystalline states are drastically different. This allows us to implement different levels of crystallization so that each region can have not just two states but potentially several states. This type of storage where one region can have multiple states is referred to as MultiLevel Cell (MLC) storage.
Since phase change memory implementations are quite expensive to produce it is believed that a significant implementation of MLC storage will allow for very large amounts of storage and justify the high price of the technology in a competitive market. Of course, MLC storage isn’t unique to phase change memory implementations; it’s also seen in flash based memory. In flash based memory storage solutions it’s common to see four states supported per cell. This provides two bits of storage for each cell – as opposed to one bit per sell for Single Level Cell (SLC) storage.
Figure 1: attributes of phase change memory (PCM) compared to other types (Courtesty of hothardware.com)
Other than MLC, what are some other advantages of phase change memory solutions? Well, like flash, there are no moving parts which increase longevity and usability. Also, since the cell states are changed with heat via an electric pulse, there is no danger in having small magnets in close proximity to the memory. Also, these electrical pulses can change the states very quickly which can result in significantly faster write times when compared with flash.
There are some drawbacks to MLC storage. Since there are more states stored in a single cell there is less of a difference between these states which can result in a higher bit error rate (BER). In flash based memory storage solutions this can be adequately handled via an increased role for error correction modules. The increased error correcting could potentially slow down an application, but this is the trade off for getting basically double the storage in the physical area.
In phase change memory the effect of having four states per cell is even more dramatic than in the flash based implementations. This is due to the cells having what’s known as a resistance drift. A resistance drift describe the effect of the resistance level of the different states chaning – or drifting – over time.
So you may be asking – what’s the big deal about this resistance drift? Can’t we just store a known value in some cells and measure the drift over time, then compensate for the drift when reading from the other cells? Yes, we could, if the drift was uniform across the cells. It’s not. The resistance drift is somewhat erratic and cannot be compensated for in this manner.
IBM scientists have recently developed a new technique for countering this resistance drift observed in phase change memory systems. Their system relies on their findings that while the resistance level for each state drifts, the order of resistivity of the states stays the same – for the most part. For instance, if state 1 is less resistive than state 2, it will remain less resistive than state 2 even after a significant amount of drift occurs.
This allows data to be encoded not in the programmed state but in the relative order of the states in a small group of cells. Using this type of encoding scheme errors will only be seen when the resistivity levels of states cross. For example, if state 1 becomes more resistive than state 2. This effect does happen, but it happens relatively infrequently – especially for small groups of cells. If errors are detected while using such an encoding scheme typical software-based error correction methodologies can be applied effectively. Using this technique does come at the expense of reduced storage capacity. Where a four level MLC implementation can allow for two bits to be stored per cell the method implemented by IBM scientists only utilized 1.57 bits per cell. While this is quite a reduction compared to the full MLC capabilities it is still a significant improvement in storage capacity compared to the SLC implementations.
The paper produced by the IBM scientists which can be found here, includes some very impressive results. For example using there technique and comparing it to a reference cell technique similar to what I described earlier they observed a significant improvement in BER detection. After 30 days their method saw a BER of around 1/100000 which is significantly less than the BER seen using the reference cell technique which was about 1/1000.
This breakthrough developed by IBM is significant. With more scientists working with this technique and applying their own theories and implementations I’m sure that the BER of such techniques will continue to improve. Combing this with advances in manufacturing processes phase change memory will soon become a competitive solution for high performance implementations.
Another challenge for phase change memory implementations is the preciseness required when setting the state of a cell. Since the state is changed via the heat created from an electric pulse, there is the risk that the heat will transfer to adjacent cells and change their state resulting in a higher BER. This can be mitigated with proper manufacturing techniques but is an example of the challenges faced by this technology.