OSI Reference Model: Layer 4 Hardware

If you would like to read the other parts in this article series please go to:

• OSI Reference Model: Layer 1 Hardware
• OSI Reference Model: Layer 2 Hardware
• OSI Reference Model: Layer 3 Hardware

If you would like to be notified when Russell Hitchcock releases the next article in this series please sign up to the WindowsNetworking.com Real time article update newsletter.

The Transport layer provides the functionality to transfer data from one end point to another across a network. The Transport layer is responsible for flow control and error recovery. The upper layers of the OSI Reference Model see the Transport Layers as a reliable, network independent, end-to-end service. An end-to-end service within the transport layer is classified in one of five different levels of service; Transport Protocol (TP) class 0 through TP class 5.

TP class 0 is the most basic of the five classification levels. Services classified at this level perform segmentation and reassembly.

TP class 1 services perform all of the functions of those services classified at TP class 0 as well as error recovery. A service at this level will retransmit data units if they were not received by the intended recipient.

TP class 2 services perform all of the functions of those services classified at TP class 1 as well as multiplexing and demultiplexing, more on this below.

 

TP class 3 services perform all of the functions of those services classified at TP class 2 as well as sequencing of the data units to be sent.

TP class 4 services perform all of the functions of those services classified at TP class 3 as well as the ability to provide its services over either a connection oriented or connectionless network. This class of Transport Protocols is the most common and is very similar to the Transmission Control Protocol (TCP) of the Internet Protocol (IP) suite.

I say that TP class 4 is very similar to TCP because there are some key differences. TP class 4 uses 10 data types while TCP uses only one. This means that TCP is simpler but also means that it must contain many headers. TP class 4, while more complicated, can contain one quarter of the headers that TCP contains which obviously reduces a lot of overhead.

Connection oriented networks are like your telephone. A connection is made before data is sent and is maintained throughout the entire process of sending data. With this type of network, routing information only needs to be sent while setting up the connection and not during data transmission. This reduces a lot of overhead which improves communication speed. This type of communication is also very good for applications, like voice or video communications, where the order of the data received is especially important.

Connectionless networks are the opposite of connection oriented networks, in that they do not set up a connection prior to sending data. Nor do they maintain any connection between two end points. This requires that routing information is sent with each packet, which therefore increases the communication overhead.

Keep in mind that just because data is being sent in packets does not mean that it is a connectionless network; virtual circuits are an example of a connection oriented network that use packets.

Since, in my previous articles, I have already covered aspects of error detection and recovery and since this article is focused on hardware I am going to give a basic introduction to a widely known (yet poorly understood) aspect of the Transport Layer; multiplexing and demultiplexing.

Multiplexing (or muxing as it is often referred to) is one of those words that people often hear while not really understanding what it means. Many people may know that muxing is the process of combining two or more signals into one signal, but how exactly is that done? Well, there are multiple ways in which this can be done. Digital signals can be muxed in one of two ways, time-division multiplexing (TDM) and frequency division multiplexing (FDM). Optical signals use a method called wavelength-division multiplexing, although this is the same thing as FDM (wavelengths of course being inversely proportional to frequency).

To demonstrate how muxing works, let's take a simple case of TDM. In this example let's assume a two signal input. A two input muxing device will require three inputs; one for each of the signals and one for the control signal. A two input muxing device will also have one output. This device will alternate between the two input signals putting the resulting signal onto its output.
 
 
 
Figure 1: Logic gate schematic of a two input mux. Courtesy of www.cs.uiowa.edu
 

Figure 1, above, shows a two input mux. The two signals are represented as d0 and d1 while the control signal is represented as c. The output, which is a function of the two inputs, is represented as f. The symbols in this figure are standard symbols for representing logic gates. Figure 2, shows the meaning of these three gates. 
 

Figure 2: Basic logic gates. Courtesy of www.cs.uiowa.edu
 

The mux works by receiving a digital signal on the c input. This c signal goes directly to one input of the 1 'AND' gate, and to the 'NOT' gate. The 'NOT' gate inverts the signal and then sends it to one input of the 2 'AND' gate. The outputs of the 'AND' gates will only be high when the control signal and the input signal (d0 or d1) are high. Since the control signal is sent through a 'NOT' gate prior to reaching the 2 'AND' gate only one of the two 'AND' gates will see a high control signal at any one instant in time. This process means that f will alternate between being equal to d0 and then to d1 at the frequency of c.

 

Now you might be thinking "that's great, but who cares about getting half the signal". Well, that does not necessarily have to be the case. If the frequency of the control signal is at least twice the frequency of input signals, then the output f will contain enough information about both d0 and d1 that a demuxer will be able to reconstruct the original input signals. This is the core idea of the Nyquist-Shannon sampling theorem.

 

Looking at the logic gates in Figures 1 and 2 those of you with programming or scripting experience will recognize these logic functions as common tools in a programmer’s repertoire. Keep in mind that while these functions are found in software programs, I am strictly talking about hardware functions which are carried out with a series of transistors, acting as switches, arranges in clever ways to achieve these logic functions.

A demuxer is basically the opposite of a muxer. A demuxer will have one input signal, and in the case described above will have two output signals. A demuxer, of course, also has a control signal although with demuxers it is often called the addressing signals. This control signal is called an address signal because the demuxing circuit can also be used to simply choose which output pin to put the input signal on to.

In my next article I will discuss the fifth layer of the OSI Reference Model. Until then, and as always, if you have any questions about this or any other article of mine, do not hesitate to send me an email; I will do my best to get back to you.

If you would like to read the other parts in this article series please go to:

• OSI Reference Model: Layer 1 Hardware
• OSI Reference Model: Layer 2 Hardware
• OSI Reference Model: Layer 3 Hardware

If you would like to be notified when Russell Hitchcock releases the next article in this series please sign up to the WindowsNetworking.com Real time article update newsletter.